Intel has taken the wraps off a secret technique it is using to
increase the speed of its Pentium and Centrino chips. The technique
boosts the rate at which transistors switch, without having to make
The announcement, at the International Electron Devices Meeting
in Washington DC last week, gives a glimpse into the intensely
secretive way chip firms attempt to gain an edge over their
competitors in a market worth over $100 billion a year.
Chip speed ultimately depends on the rate at which transistors
can switch on and off. This in turn depends on the speed at which
current can flow through them, and the distance the charge has to
The current speed is determined by the material through which it
flows - and since chipmakers are more or less stuck with silicon,
they have concentrated on increasing switching speed by making
But the industry is finding it increasingly difficult to reduce
size further. Intel's new technique increases the speed of current
flow by deforming the crystal structure of silicon. The company
announced that it would be selling chips that employed "strained
silicon" in 2002. "But we did not explain how we did it," says Mark
Bohr, a senior research fellow at Intel in Santa Clara,
The speed of current flow depends on the crystal structure of
silicon. Inside the silicon lattice, the electrons around each atom
form patterns of energy states called orbitals. These states merge
to form a continuous band that allows electrons and positively
charged "holes" to move through the lattice.
The orientation of the orbitals is important. Each atom has six
lobe-shaped orbitals: two in the direction of electron flow and four
that are perpendicular to it (see graphic).
In ordinary silicon, all six orbitals have the same energy so
there is no preferred direction of flow. But stretching the lattice
decreases the energy of the two orbitals in that direction, letting
electrons flow more easily along the aligned orbitals. Similarly,
squeezing the lattice lets positive charges to flow more easily.
Turning this to practical advantage is difficult, though.
Transistors contain regions of silicon that are doped with a
material such as phosphorus to create an excess of electrons in the
conduction band - "n-doped" silicon - and regions that are doped
with boron, which adds positively-charged holes to form "p-doped"
Intel's trick is to stretch the n-doped areas while compressing
the p-doped ones.
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Bohr says the company compresses p-doped regions by carving
trenches along their opposite ends and filling them with silicon
germanium, which has a larger lattice size than silicon alone and so
compresses the regions nearby. This improves hole conduction by 25
To stretch the silicon lattice, Intel deposits a film of silicon
nitride over the whole transistor at high temperature. Because
silicon nitride contracts less than silicon as it cools, it locks
the silicon lattice beneath it in place with a wider spacing than it
would normally adopt. This improves electron conduction by 10 per
Intel says the approach gives it a significant speed advantage
over its competitors and is using the technique in its latest
generation of chips, whose individual features are as small as 90
nanometres. Intel claims its technique boosts chip performance by up
to 20 per cent compared with ordinary chips of the same size.
"Intel's performance is pretty impressive," says Judy Hoyt, a
physicist at the Massachusetts Institute of Technology, who
pioneered the strained-silicon idea in 1992. She adds that other
strained-silicon techniques are likely to emerge soon. IBM says it
is now planning to introduce strained silicon in its 90-nanometre